1. Field of the Invention
The present invention relates to debugging of integrated circuits, and in particular to debugging of integrated circuits that include hardware blocks that are implemented in programmable logic.
2. Description of Related Art
Programmable logic devices (“PLDs”) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs typically include blocks of logic elements, sometimes referred to as logic array blocks (“LAB s”; also referred to by other names, e.g., “configurable logic blocks,” or “CLBs”). Logic elements (“LEs”, also referred to by other names, e.g., “logic cells”) may include a look-up table (LUT) or product term, carry-out chain, register, and other elements. LABs (comprising multiple LEs) may be connected to horizontal and vertical lines that may or may not extend the length of the PLD.
PLDs have configuration elements that may be programmed or reprogrammed. Configuration elements may be realized as RAM bits, flip-flops, EEPROM cells, or other memory elements. Placing new data into the configuration elements programs or reprograms the PLD's logic functions and associated routing pathways. Configuration elements that are field programmable are often implemented as RAM cells (sometimes referred to as “CRAM” or “configuration RAM”). However, many types of configurable elements may be used including static or dynamic random access memory, electrically erasable read-only memory, flash, fuse, and anti-fuse programmable connections.
Some PLDs include a processor with fixed hardware, and some configurable hardware that is external to the processor. Such external hardware (e.g. FPGA or other configurable hardware) may be configured as hardware blocks that perform particular operations for the processor. The hardware blocks provide an alternative to performing those operations by software in the processor. In many cases, operations can be performed faster by such hardware blocks than by processor software, thus improving overall performance. When a particular operation is identified as suitable for implementation in a hardware block, the software code for that operation may be used as source code to configure the hardware block. Such conversion from source code to a hardware block in an FPGA or other configurable circuitry may be performed in an automated manner.
In some cases, when software for a processor is implemented using external hardware blocks for some operations, debugging the resulting integrated circuit may be difficult. In particular, conventional software debugging does not facilitate debugging hardware, while hardware debugging does not facilitate software debugging. Generally, hardware and software debugging are performed separately, in isolation from each other, which may be time consuming and may require personnel with two different skill sets (e.g. software engineers may not be familiar with hardware debugging, and hardware engineers may not be familiar with software debugging.)